To date, conventional semiconductor memory chips such as DRAMs neither employ frames for data transfer nor include a frame decoder. Moreover, conventional semiconductor memory chips widely are operated asynchronously, which results in a number of disadvantages.
In future memory systems and semiconductor memory chips, it is expected that data will be transmitted at very high frequency. The data transfer will likely be ruled by a protocol, and data bits will be organized in frames in accordance with the protocol. After several alignment procedures, for exempla, a data stream is demultiplexed in the memory chip to a lower frequency and ready for evaluation. Such a novel semiconductor memory chip must include a frame decoder to decode the signal frames to: (a) memory relevant commands; (b) system commands; and (c) write data to be intermediately stored in an intermediate data buffer.
In such a system, each frame can contain one or more memory relevant commands. Commands dedicated to the same memory bank can be placed in different frames. For special command types, one frame may even contain commands to different banks which are called interbank commands. Moreover, data has to be synchronized with decoded commands provided from the frame decoder to the memory core. In order to reduce latency, the frame decoder unit is operated at a frequency higher than the actual memory core's operating frequency. This implies a potential risk of data collision when using the same busses.
For such a frame decoder unit several requirements exist. Handling of complex functionality is one such requirement. Compared to conventional semiconductor memory chips such as DRAM chips, the functionality of the proposed semiconductor memory chips is greatly increased. Main building blocks have to be arranged in such a way that safe handling of functional complexity is possible. Further, there is a need for a detailed specification. Interfaces, especially internal ones always represent a potential design risk. A synchronous frame decoder containing major parts of the conventional asynchronous memory chip logic is easier to specify and therefore safer. Verification requirements are another consideration. Higher functional complexity goes along with special verification methods that are beyond transistor level oriented methods. However, the opportunity to employ such methods depends on certain arrangements.
Further, from a plan layout perspective, that is, the arrangement within the chips area of the main memory blocks, namely the memory banks, for the frame decoder which forms a link between the memory banks and the reception interface section a number of restrictions exist: memory banks can be arranged in a split and a grouped manner; and control signals to the memory banks must be placed in such a way that wire length, timing, power consumption and area impact are optimized jointly.